preliminary data sheet FX060 frequency translator features 19.44 mhz and 155.52 mhz clock outputs locked to an 8 khz or 1.544 mhz input clock commercial or industrial temperature range surface mount option available single 5.0 vdc supply ac/hcmos compatible inputs and outputs lock detect circuit <10 ps rms output jitter at 19.44 mhz 19 ps rms typical output jitter at 155.52 mhz ppm input frequency tolerance applications clock frequency translation sonet/sdh/atm clock distribution description vectron s FX060 frequency translator is a low noise, narrow band pll that generates 155.52 mhz and 19.44 mhz output clocks locked to an input 8 khz or 1.544 mhz reference clock. the 19.44 mhz clock is generated by a low noise vcxo. the 155.52 mhz signal is a multiplied representation of the 19.44 mhz output. block diagram phase detector frequency divider loop filter 19.44 mhz vcxo frequency multiplier lock detect 19.44 mhz output 155.52 mhz output 8 khz input user connection when 1.544 mhz input is used 8 khz output 1.544 mhz input frequency divider *this bulletin is provided for informational purposes to enable early engineering discussions. it should not be assumed that the product described in this document is qualified or available for manufacture.
FX060 frequency translator vectron international reserves the right to make changes to the product(s) and/or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such prod uct(s) or information. printed in usa 2/99 1.38 12 13 .73 .225 .007 .051 .004 .019 .036 .116 924 .600 .28 max .010x.024 .39 .105 .max thru-hole option j-lead option 24 1 .100 .140 .80 .600 typ. typ. see note 2 1. pin numbers are for ref only. they do not appear on the unit. 2. components are mounted below in this area and not to exceed dim. shown. table 1. performance characteristics parameter symbol minimum typical maximum units supply voltage v dd 4.75 5.0 5.25 v supply current i dd - 60 100 ma input signal clkin ac/hcmos - output load clkout ac/hcmos - output symmetry dc 45 50 55 % 19.44 mhz output clock edge jitter j 19.44 - - 10 ps rms 155.52 mhz output clock jitter j 155.52 - 19 - ps rms rise/fall time of 19.44 mhz output t r/f --7ns rise/fall time of 155.52 mhz output t r/f --2ns input frequency tolerance - -70 - +70 ppm output frequency stability tracks reference stability when locked performance characteristics outline drawing dimensions are in inches table 2. pin function pin symbol function 1 out19 19.44 mhz clock output 3 out155 155.52 mhz clock output 10 l ock lock detect output. lock indicated by logic high. when not locked output toggles at a rate proportional to the phase difference between the input clock and the internal crystal oscillator . 14 out8 8 khz clock output from 1.544 mhz reference clock 15 in8 8 khz reference clock input. 22 in1.5 1.544 mhz r eference clock input* 24 vdd 5 vdc supply 2,6,12,19 gnd case ground 4,5,7,8,9, 11,13,16, n/c no user connection 17,18,20, 21, 23 handing precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (esd) during handling and mounting. how to order FX060 j = j lead t = thru hole c = to l = to
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